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1 gmm77316380ctg-5/6 16,777,216 words x 72 bit cmos dynamic ram module * this data sheet is subject to change without notice. description the gmm77316380ctg is an 16m x 72 bits dynamic ram module which is assembled 18 pieces of 16m x 4bit drams in 32 pin tsop package and two 16bit driver ics in 48pin tssop package mounted on a 168 pin printed circuit board with decoupling capacitors. the gmm77316380ctg is optimized for application to the systems which are required high density and large capacity such as main memory of the computers and an image memory systems, and to the others which are requested compact size. the gmm77316380ctg provides common data inputs and extended data outputs. features ? 168 pins dual in-line package - gmm77316380ctg : gold plating ? extended data ouput (edo) mode capability ? single power supply ? fast access time & cycle time ? low power active : 9144/8496mw (max) standby : 105mw (cmos level : max) ? ras only refresh, cas before ras refresh, hidden refresh capability ? all inputs and outputs ttl compatible ? 8192 refresh cycles/64ms ( unit: ns ) gmm77316380ctg-5 t rac t cac t rc t hpc 50 60 20 104 25 gmm77316380ctg-6 ? gmm77316380ctg (both side) pin symbol pin symbol pin symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 pin symbol 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 v ss dq 0 dq 1 dq 2 dq 3 v cc dq 4 dq 5 dq 6 dq 7 dq 8 v ss dq 9 dq 10 dq 11 dq 12 dq 13 v cc dq 14 dq 15 dq 16 dq 17 v ss rsvd rsvd v cc /we 0 /cas 0 v ss dq 36 dq 37 dq 38 dq 39 v cc dq 40 dq 41 dq 42 dq 43 dq 44 v ss dq 45 dq 46 dq 47 dq 48 dq 49 v cc dq 50 dq 51 dq 52 dq 53 v ss rsvd rsvd v cc rfu /cas 1* dq 22 dq 23 v cc dq 24 rfu rfu rfu rfu dq 25 dq 26 dq 27 v ss dq 28 dq 29 dq 30 dq 31 v cc dq 32 dq 33 dq 34 dq 35 v ss pd 1 pd 3 pd 5 pd 7 id 0 v cc rsvd /ras 0 /oe 0 v ss a 0 a 2 a 4 a 6 a 8 a 10 a 12 v cc rfu rfu v ss /oe 2 /ras 2 /cas 4 rsvd /we 2 v cc rsvd rsvd dq 18 dq 19 v ss dq 20 dq 21 pin configuration (top view) pin symbol 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 rsvd /ras 1* rfu v ss a 1 a 3 a 5 a 7 a 9 a 11 a 13* v cc rfu b 0 v ss rfu /ras 3* /cas 5* rsvd /pde v cc rsvd rsvd dq 54 dq 55 v ss dq 56 dq 57 pin symbol 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 dq 58 dq 59 v cc dq 60 rfu rfu rfu rfu dq 61 dq 62 dq 63 v ss dq 64 dq 65 dq 66 dq 67 v cc dq 68 dq 69 dq 70 dq 71 v ss pd 2 pd 4 pd 6 pd 8 id 1 v cc note : pins marked * are not used in this module. speed 18 84 20
lg semicon gmm77316380ctg-5/6 2 block diagram dq 0 dq 36 dq 37 dq 38 dq 39 dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 52 dq 53 dq 54 dq 55 dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 dq 64 dq 65 dq 66 dq 67 dq 68 dq 69 dq 70 dq 71 v cc v ss 0.22 uf capacitor d0~d17, buffer dq 0 dq 0 dq 1 dq 2 dq 3 d9 dq 0 dq 1 dq 2 dq 3 d10 dq 0 dq 1 dq 2 dq 3 d11 dq 0 dq 1 dq 2 dq 3 d12 dq 0 dq 1 dq 2 dq 3 d13 dq 0 dq 1 dq 2 dq 3 d14 dq 0 dq 1 dq 2 dq 3 d15 dq 0 dq 1 dq 2 dq 3 d16 dq 0 dq 1 dq 2 dq 3 d17 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dq 32 dq 33 dq 34 dq 35 dq 48 dq 49 dq 50 dq 51 dq 1 dq 2 dq 3 d0 dq 0 dq 1 dq 2 dq 3 d2 dq 0 dq 1 dq 2 dq 3 d3 dq 0 dq 1 dq 2 dq 3 d4 dq 0 dq 1 dq 2 dq 3 d5 dq 0 dq 1 dq 2 dq 3 d6 dq 0 dq 1 dq 2 dq 3 d7 dq 0 dq 1 dq 2 dq 3 d8 dq 0 dq 1 dq 2 dq 3 d1 v cc v ss 2.2 uf tantal capacitor + drams: d0~d17 a1~a12 a0 b0 drams: d0~d8 drams: d9~d17 vss pde ( when= 0, 1= nc) d0~d17, buffer oe0 we0 cas0 ras0 a1~a12 cas4 ras2 oe2 we2
lg semicon gmm77316380ctg-5/6 3 pin description pin function pin function a0,b0,a1-a12 dq0-dq71 v cc v ss nc address inputs data input/output row address strobe column address strobe read/write enable power (+3.3v) ground no connection ras0, ras2 cas0, cas4 we0, we2 pde presence detect enable pd 1~8 presence detect id 0~1 id bit rsvd reserved use rfu reserved for future use oe0, oe2 output enable presence detect pins ( optional) pin 50 ns 60 ns pd1 pd2 1 pd3 pd4 1 1 1 1 1 1 1 pd5 pd6 1 0 1 1 0 pd7 pd8 0 0 1 0 id0 id1 0 0 0 absolute maximum ratings* * note: 1. stress greater than above absolute maximum ratings may cause permanent damage to the device. recommended dc operating conditions (t a = 0 ~ 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 3.6 typ 3.3 - - min 3.0 note 1 1 1 symbol parameter rating unit t a t stg v in /v out 0 ~ 70 -55 ~ 125 -0.5 ~ 4.6 ambient temperature under bias storage temperature (plastic) voltage on any pin relative to v ss v i out 50 short circuit output current ma p d 21 power dissipation w c c 2.0 -0.3 vcc +0.3 0.8 vcc voltage on vcc pin relative to v ss -0.5 ~ 4.6 v * note: 1. all voltages referenced to v ss .
lg semicon gmm77316380ctg-5/6 4 dc electrical characteristics: (v cc = 3.3v+/-0.3v, t a = 0 ~ 70c) note: 1. i cc depends on output load condition when the device is selected. i cc(max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . unit note v v ua ua ? ? ? ? ? ? ? 1,2 1,3 2 1 symbol parameter v oh v ol output level output ``h`` level voltage (i out = -2 ? ) output level output ``l`` level voltage (i out = 2 ? ) i cc1 operating current average power supply operating current (ras, cas cycling: t rc = t rc min) i cc2 standby current (ttl) power supply standby current (ras, cas = v ih , d out = high-z) i cc3 ras-only refresh current average power supply current ras-only refresh mode (ras cycling, cas = v ih , t rc = t rc min) i cc4 extended data out mode current average power supply current extended data out mode (ras = v il , cas, address cycling: t pc = t pc min ) i cc5 standby current (cmos) power supply standby current (ras, cas>=v cc -0.2v, d out = high-z) i cc6 cas-before-ras refresh current ( t rc = t rc min) i cc7 standby current i i(l) i o(l) input leakage current, any input (0v v in vcc ) output leakage current (d out is disabled, 0v v out vcc ) ras = v ih cas = v il d out = enable gmm77316380ctg min max 50 ns 60 ns 2.4 0 - - - - - - - - - - - -5 -5 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns vcc 0.4 2540 2360 2540 2360 2540 2360 56 2000 1820 29 110 5 5
lg semicon gmm77316380ctg-5/6 5 capacitance (v cc = 3.3v+/-0.3v, t a = 25c, f = 1mhz) symbol parameter note unit max min c i1 c i2 c 13 input capacitance (a0~a12,b0) input capacitance (we0, we2, oe0, oe2) input capacitance (ras0,ras2) 1 1, 2 1, 2 pf pf pf 20 20 65 - - - c 14 input capacitance (cas0,cas4) 1, 2 pf 20 - c i/o i/o capacitance (dq0~dq71) 1, 2 pf 20 - note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable d out . ac characteristics (v cc = 3.3v+/-0.3v, t a = 0 ~ 70c, notes 1, 2,19) test conditions input rise and fall times : 2ns output timing reference levels : v ol /v oh = 0.8/2.0v input level : v il /v ih = 0.0/3.0v output load : 1 ttl gate+c l (100pf) input timing reference levels : v il /v ih = 0.8/2.0v (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) symbol max max min t rc t rp t ras t cas t asr t rah t asc t cah t rcd 4 t rad 3 t rsh t csh t crp min 84 30 50 8 5 8 0 8 12 10 18 35 10 - - 10000 - - - - 32 20 - - - unit notes ? ? ? ? ? ? ? ? ? ? ? ? ? t t t ref refresh period ( 8192 cycles) 2 - 50 64 ? ms t odd t dzo t dzc 18 0 0 - - - ? ? ? 60 10 104 - 40 - 10000 5 - 10 - 0 - 10 - 14 40 12 25 20 - 40 - 10 - 20 - 0 - 0 - 2 50 - 64 t cp 8 - ? 10 - 10000 10000 gmm77316380ctg-5 gmm77316380ctg-6 parameter random read or write cycle time ras precharge time ras pulse width cas pulse width row address set-up time row address hold time column address set-up time column address hold time ras to cas delay time ras to column address delay time ras hold time cas hold time cas to ras precharge time transitiontime (rise and fall) oe to d in delay time oe delay time from d in cas set-up time from d in cas precharge time 5 6 6 7
lg semicon gmm77316380ctg-5/6 6 read cycles symbol max max min min - - - 0 0 0 30 50 18 30 - - - unit notes ? ? ? ? ? ? ? ? - t rac t cac t aa t rcs t rch t rrh t ral t cal 8,9 t oac - 18 - 20 ? - 60 - 20 - 35 0 - 0 - 0 - 35 - 18 - 15 - 9,10,17 ? ? t rdd t wdd ? t ofr ? t wez - 15 - 15 15 - - 15 - 13 - 13 13 - 13 - ? ? ? t clz t oh t cdd cas to output in low - z 18 - ? ? t ohr t oez ? t off 20 - - 20 - 20 - 3 - - 2 18 - 18 - 3 - - - ? t rchr 60 - 50 - ? t oho 3 - 3 - 2 9 3 3 gmm77316380ctg-5 gmm77316380ctg-6 parameter access time from ras access time from cas access time from column address read command set-up time read command hold time to cas read command hold time to ras column address to ras lead time column address to cas lead time access time from oe ras to d in delay time output buffer turn-off delay time from ras output buffer turn-off delay time from we output data hold time cas to d in delay time output data hold time from ras output buffer turn-off delay time from oe we to d in delay time read command hold time from ras output buffer turn-off delay time from cas 9,11,17 12 12 13,21 13 5 13 21 13,21 21 output data hold time from oe
lg semicon gmm77316380ctg-5/6 7 wrtie cycles read-modify-write cycles t rwc t rwd t cwd t awd refresh cycle symbol max max min min 116 72 30 42 - - - - unit notes ? ? ? ? refresh cycles t csr symbol cas set-up time (cas-before-ras refresh cycle) t chr cas hold time (cas-before-ras refresh cycle) parameter max max min min 5 - unit notes ? 8 - - ? ? t oeh 13 - ? 140 84 34 49 15 - - - - - 14 5 10 10 - - t rpc ras precharge to cas hold time 5 - ? 5 - - t wcs t wch t wp t rwl t cwl t ds t dh symbol write command set-up time write command hold time write command pulse width write command to ras lead time write command to cas lead time data-in set-up time data-in hold time parameter max max min min 0 8 8 8 0 13 - - - - - - unit notes ? ? ? ? ? ? ? - 14 15 15 0 10 10 10 0 15 - - - - - - - read-modify-write cycle time ras to we delay time cas to we delay time column address to we delay time parameter oe hold time from we 18 20 14 14 gmm77316380ctg-5 gmm77316380ctg-6 gmm77316380ctg-5 gmm77316380ctg-6 gmm77316380ctg-5 gmm77316380ctg-6 21 t wrp we setup time (cas-before-ras refresh cycle) t wrh we hold time (cas-before-ras refresh cycle) 5 8 5 ?
lg semicon gmm77316380ctg-5/6 8 - - 28 ? ? - - 35 33 - 100000 ? 40 - 100000 t rasp t acp t rhcp 28 - ? 35 - 8 5 - - ? ? 10 5 - - 5 - ? ? 5 - 8 - 10 - t col t cop t oep t rchp edo mode ras pulse width access time from cas precharge ras hold time from cas precharge oe precharge time cas hold time referred oe cas to oe set-up time read command hold time from cas precharge output data hold time from cas low 16 max max min min 20 8 - - unit notes ? ? 25 10 - - extended data out mode cycles t hpc t wpe symbol edo page mode cycle time write pulse width during cas precharge parameter gmm77316380ctg-5 gmm77316380ctg-6 t doh max max min min 57 45 - - unit notes ? ? 68 54 - - edo page mode read-modify-write cycle t hprwc t cpw symbol edo page mode read-modify-write cycle time we delay time from cas precharge parameter gmm77316380ctg-5 gmm77316380ctg-6 20 9,17 9,22 14 present detect read cycle symbol max max min min unit notes ns ? gmm77316380ctg-5 gmm77316380ctg-6 t pd t pdoff parameter pde to valid pd bit pde to pd bit in active 10 10 7 7 2 2
lg semicon gmm77316380ctg-5/6 9 notes: ac measurements assume t t = 2 ? . ac initial pause of 200 us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing ras-only refresh or cas-before- ras refresh) operation with the t rcd ( max) limit insures that t rac ( max) can be met, t rcd ( max) is specified as a reference point only: if t rcd is greater than the specified t rcd ( max) limit, then access time is controlled exclusively by t cac . operation with the t rad ( max) limit insures that t rac ( max) can be met, t rad ( max) is specified as a reference point only: if t rad is greater than the specified t rad ( max) limit, then access time is controlled exclusively by t aa . either t oed or t cdd must be satisfied. either t dzo or t dzc must be satisfied. v ih ( min) and v il ( max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih ( min) and v il ( max). assumes that t rcd <= t rcd ( max) and t rad <= t rad ( max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. measured with a load circuit equivalent to 1 ttl loads and 100 pf . assumes that t rcd >= t rcd ( max) and t rcd + t cac ( max) >= t rad + t aa ( max). assumes that t rad >= t rad ( max) and t rcd + t cac ( max) <= t rad + t aa ( max). either t rch or t rrh must be satisfied for a read cycles. t off ( max), t oez( max), t ofr ( max) and t wez ( max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. t wcs , t rwd , t cwd, t awd, and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only: if t wcs >= t wcs ( min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if t rwd >= t rwd ( min), t cwd >= t cwd ( min), t awd >= t awd ( min) and t cpw >= t cpw ( min), the cycle is a read- modify-write and the data output will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. t ds and t dh are referred to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. t rasp defines ras pulse width in extended data out mode cycles. access time is determined by the longest among t aa, t cac and t cpa . in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc / v ss line noise, which causes to degrade v ih min/v il max level. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.
lg semicon gmm77316380ctg-5/6 10 t hpc ( min) can be achieved during a series of edo mode early write cycles or edo mode read cycles. if both write and read operation are mixed in a edo mode, ras cycle { edo mode mix cycle (1),(2) } minimum value of cas cycle t hpc ( t cas + t cp + 2 t t ) becomes greater than the specified t hpc ( min) value. data output turns off and becomes high impedance from later rising edge of ras and cas. hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . t doh defines the time at which the output level go cross. v ol =0.8 v, v oh =2.0 v of output timing reference level. before and after self refresh mode, execute cbr refresh to all refresh addresses in or within 64 a period on the condition a and b below. a. enter self refresh mode within 15.6 us after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6 us after exiting from self refresh mode. in case of entering from ras-only-refresh, it is necessary to execute cbr refresh before and after self refresh mode according as note 23. for l_version, it is available to apply each 128 a and 31.2 us instead of 64 a and 15.6 us at note 23. at t rass ? 100 us , self refresh mode is activated, and not activated at t rass ? 10 us . it is undefined within the range of 10 us ? t rass ? 100 us . for t rass ? 10 us , it is necessary to satisfy t rps . xxx: h or l ( h : v ih ( min) <= v in <= v ih ( max), l: v ih ( min) <= v in <= v ih ( max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il. 20. 21. 22. 23. 24. 25. 26. 27. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2).
lg semicon gmm77316380ctg-5/6 11 timing waveforms figure 1. read cycle * : don`t care t rc t ras t rp ras t csh t crp t rcd t rsh t cas t t t rad t ral t asr t rah address row column t rcs t rch t rrh we t asc t cah d out d out d in t dzc t cdd high-z t oed oe t dzo t oac t cac t aa high-z t rac t oez t off cas
lg semicon gmm77316380ctg-5/6 12 figure 2. early write cycle t wcs t wch * : don`t care we d out ** oe : don`t care d in t ds t dh high-z t rc t ras t rp ras t csh t crp t rcd t rsh t cas t t cas t asr t rah t asc t cah address column row *** t wcs t wcs (min) > = d in
lg semicon gmm77316380ctg-5/6 13 figure 3. delayed write cycle t rc t ras t rp ras t csh t crp t rcd t rsh t cas t t cas t asr t rah t asc t cah address column t rcs * : don`t care we d out row d in t wp t rwl t cwl t oed t oeh invalid output d in oe ** invalid d out comes out, when oe is low level. t dzc t dh t ds high-z t dzo t oez ** high-z
lg semicon gmm77316380ctg-5/6 14 figure 4. read modify write cycle t rwc t ras t rp ras t crp t rcd t t t asr t rah t asc t cah address column * : don`t care we row d in t wp t rwl t cwl t oed t oeh d in t dzc t dh t ds high-z t rad t cwd t awd t rwd t rcs t dzo d out d out t oac oe t oez t cac t aa t rac cas t cas high-z
lg semicon gmm77316380ctg-5/6 15 figure 5. ras only refresh cycle ras cas address row d out high-z t asr t rah t crp t rpc t rp t ras t rc t t figure 6. cas before ras refresh cycle t crp ras t rp t t cas d out high-z t off t ras t rp t ras t rp t rc t rc t cpn t rpc t csr t chr t cpn t rpc t csr t chr t crp address * ** we : v ih : don`t care * oe,we : don`t care ** rrfresh address : a0~a12 (ax0 ~ ax12) invalid d out
lg semicon gmm77316380ctg-5/6 16 figure 7. hidden refresh cycle ras t ras t t * : don`t care t rc t rc address we t rp t ras t rp t ras t rp t rc t rcd t rsh t chr t crp t rad t ral column row t asr t rah t asc t cah t rcs d out d out oe d in high-z t cas t rrh t rch t dzc t cac t aa t rac t dzo t oac t oed t cdd t oez t off cas ( refresh) ( refresh) ( read) high-z
lg semicon gmm77316380ctg-5/6 17 figure 8. extended data out mode read cycle cas ras address we t rasp t rp t rhcp * : don`t care row column column columnn oe t t t rcd t cas t cas t hpc t rsh t cp t asr t rah t rad t asc t asc t cah t rcs t rch t ral d out d out 1 d out 2 d out n t rac t aa t rrh t wez t ofr t off t cpa t aa t cac t cpa t aa t cac t cac t doh t doh t oez t oac t asc t cah t cas t cp high-z t rchc t rcha t ohr t oh t csh t crp t csh t cah
lg semicon gmm77316380ctg-5/6 18 ras address we oe d out cas row column 1 column 2 column n d out 1 d out 2 high-z d out 3 d out n d out 2 t t t cas t csh t cp t hpc t rac t aa t cac t oac t asr t rah t cah t cp t cas t cas t hpc t cp t cas t rsh t cprh t hpc t rp t rasp t crp t rch t rcs t rchr t cal t asc t cah t asc t cah t asc t cah t ral t cal t cal t cal t col t cop t aa t cac t wez t oez t oac t aa t cac t doh t oez t oac t cac t aa t cpa t ofr t ohr t oez t off t oh column 3 t rch t rcs t asc t rchc t rrh t cpa t cpa figure 9. extended data out mode read cycle (oe control)* * note : edo hi-z control by oe or we. oe rising edge disables data outputs. when oe goes high during cas high, the data will not come out until next cas access. when we goes low during cas high, the data will not come out until next cas access.
lg semicon gmm77316380ctg-5/6 19 figure 10. extended data out mode early write cycle ras d in address we t t column 1 row column 2 column n t rcd t cas t csh t cp t cas t hpc t cp t cas t asr t rah t rasp t rp d in 1 d in 2 d in n d out high-z t rsh t crp t asc t cah t asc t cah t asc t cah t wcs t wch t wcs t wch t wcs t wch t ds t dh t ds t dh t ds t dh *** : don`t care oe : don`t care cas t wcs >= t wcs (min) ** *
lg semicon gmm77316380ctg-5/6 20 figure 11. extended data out mode delayed write cycle cas ras * : don`t care d in address we row d out invalid d out > ** t oeh t cwl = oe column 1 d in 1 column 2 column n t rasp t rp t t t rcd t cas t csh t cp t cas t hpc t cp t cas t rsh t crp t asr t rad t rah t asc t cah t asc t cah t rcs t rcs t cwl t cwl t rcs t cwl t rwl t dzc t wp t ds t dh t dzc t wp t ds t dh t dzc t wp t ds t dh t asc t cah t dzo t oed t oeh t dzo d in 2 t oed t dzo t oeh d in n t oed t oeh t clz t oez invalid d out t clz t oez invalid d out t oez t clz high-z
lg semicon gmm77316380ctg-5/6 21 figure 12. extended data out mode read modify write cycle * : don`t care ** t oeh t cwl > = ras d in address we row d out oe column 1 d in 1 column 2 column n t rasp t rp t t t rcd t cas t cp t cas t hprwc t cp t cas t rsh t crp t asr t rad t rah t asc t cah t asc t cah t rcs t rcs t cwl t cwl t rcs t cwl t rwl t dzc t wp t ds t dh t dzc t wp t ds t dh t wp t ds t dh t asc t cah t oed t oeh d in 2 t oed t oeh d in n t oed t oeh t rwd t awd t cwd t cpw t awd t cwd t cpw t awd t cwd t dzc t dzo t dzo t oac t cac t aa t rac t clz t oez d out 1 d out 2 d out n high-z t oac t cac t cpa t clz t oez t aa t oac t cpa t clz t oez t aa t cac t dzo cas high-z
lg semicon gmm77316380ctg-5/6 22 figure 13. extended data out mode mix cycle (1) *23 ras t rasp t rp t t t cp t cp t cas t cas t cp t cas t crp t rcd t csh t cas address row column 1 column 2 column 3 column 4 oe d in 1 d in 3 dout d out 2 d out 4 t rah t asr t cah t cah t cah t cah high - z t rdd t cdd t ds t dh t oed t doh t cac t cac t cac t wez * din t asc t asc t asc t asc t wcs t wch t ds t dh t wdd t aa t oac t cpa t cpa t aa t oez t oez t aa t oac t cpa t oh d out 3 : don`t care t off t ofr t cpw t awd t wp t rchc t rsh t rrh t rch t ral cas we high - z
lg semicon gmm77316380ctg-5/6 23 figure 14. extended data out mode mix cycle (2) *23 ras t rasp t rp t t we address row column 1 column 2 column 3 column 4 oe d in 2 d in 3 dout d out 1 d out 4 t csh t cp t cp t cas t cas t cp t cas t crp t rcd t rchr t cas t rcs t rch t wcs t wch t wp t rsh t rrh t rch t rah t asr t asc t cah t asc t asc t cah t cah t cpw t ral t asc t cah high - z t cal t cal t cal t cal t rdd t cdd t ds t dh t ds t dh t oed t col t oed t cop t aa t cac t oac t cpa t cac t oac t cpa t aa t oez t oez t cac t aa t oac t rac t wez t oez t off t oh t ofr * : don`t care din d out 3 cas high - z
lg semicon gmm77316380ctg-5/6 24 ras cas figure 16. test mode set cycle we figure 15. test mode cycle ** : don`t care * cbr or ras-only refresh *** address, d in , oe: don`t care set cycle*** test mode cycle reset cycle* normal mode ~ ~ ~ ~ ~ ~ ~ ~ * : don`t care ras cas we address d out t off high-z t ws t wh t cpn t rpc t csr t chr t rpc t crp t cpn t rp t ras t rp t rc t t invalid d out
lg semicon gmm77316380ctg-5/6 25 figure 16. cas before ras refresh counter check cycle (read) ras t t cas address * : don`t care we dout din t rc t ras t rp t cac t oep d out t aa t rac column t csr t chr t cpt t rsh t cas t crp t asc t cah t ws t wh t rch t rrh oe t cdd t dzc t dzo t oez t off t oac high-z t rcs high-z t oed
lg semicon gmm77316380ctg-5/6 26 ras t t cas address * : don`t care we dout din t rc t ras t rp column t csr t chr t cpt t rsh t cas t crp t asc t cah t ws t wh t wcs high-z d in t wch t ds t dh oe figure 17. cas before ras refresh counter check cycle (write)
lg semicon gmm77316380ctg-5/6 27 package dimension 85 168 1 84 5250(133.35) 5013.78(127.35) 1700(43.18) 1450(36.83) 2150(54.61) 450(11.43) 250(6.35) 700(17.78) 157.48(4.0) 1250(31.75) " c" " b" " a" 4550(115.57) unit: mil (mm) * (1 mil = 1/1000 inches) note : 1. tolerances on all dimensions +/-5 (0.127) unless otherwise specified. 2. thickness includes plating and / or metallization. detail "b" detail "a" 5.9(0.15) 100(2.54) min. 39.37(1.0) 50(1.27) 78.74(2.0) 39.37(1.0) detail "c" 78.74(2.0) 122.83(3.12) 39.37(1.0) 125(3.175) 125(3.175) r78.74 (2.0) r78.74 (2.0) 157.48(4.0) max. 50(1.27) 157.48(4.0) min. ( front side) ( rear side)

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